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STM32G0C1CEU6
MCU 32-Bit ARM Cortex-M0+ RISC 512kByte Flash 1.7V to 3.6V 48-Pin UFQFPN Tray
The STMicroelectronics MCU 32-Bit ARM Cortex-M0+ RISC is a versatile and efficient microcontroller designed for a wide range of embedded applications. With 512kByte of Flash memory and a voltage range of 1.7V to 3.6V, this microcontroller offers exceptional performance and low power consumption. Packaged in a compact 48-Pin UFQFPN tray, it is ideal for space-constrained designs while providing robust processing capabilities for various IoT and industrial applications.
Full Specifications
About This Product
The STMicroelectronics MCU 32-Bit ARM Cortex-M0+ RISC is a versatile and efficient microcontroller designed for a wide range of embedded applications. With 512kByte of Flash memory and a voltage range of 1.7V to 3.6V, this microcontroller offers exceptional performance and low power consumption. Packaged in a compact 48-Pin UFQFPN tray, it is ideal for space-constrained designs while providing robust processing capabilities for various IoT and industrial applications.
What is this product used for?
Suitable for design, repair, and production programs using Microcontrollers devices.
Typical Use Cases
Sourcing Support for This MPN
- MPN and package verification against your BOM or approved vendor list
- Approved-alternate and cross-reference review when the requested line is constrained
- Availability, lifecycle, and supply-risk discussion for procurement planning
- Packing, label, date-code, and requested document coordination
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STM32G0C1CEU6
STMicroelectronics
The STMicroelectronics MCU 32-Bit ARM Cortex-M0+ RISC is a versatile and efficient microcontroller designed for a wide range of embedded applications. With 512kByte of Flash memory and a voltage range of 1.7V to 3.6V, this microcontroller offers exceptional performance and low power consumption. Packaged in a compact 48-Pin UFQFPN tray, it is ideal for space-constrained designs while providing robust processing capabilities for various IoT and industrial applications.
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